This invention relates to a semiconductor integrated circuit and, more particularly, to a data holding circuit.
A programmable logic LSI (large-scale integrated circuit), exemplified in particular by FPGA (field programmable gate array)/PLD (programmable logic device) is such an LSI which holds in its inside the configuration information specifying how the hardware is to be constructed and which is designed to implement the desired hardware in accordance with commands by this configuration information.
Recently, with the Progress in the semiconductor manufacturing technology, the hardware that can be implemented by the programmable LSI is increasing in scale and, in keeping up therewith, substitution of the programmable LSI for the gate array LSI is proceeding.
Also, in the following U.S. patents:
literature (1): (U.S. Pat. No. 5,583,450, xe2x80x9cSequencer for A Time MultiPlexed Programmable Logic Devicexe2x80x9d);
literature (2): (U.S. Pat. No. 5,600,263. xe2x80x9cConfiguration Modes for A Time Multiplexed Programmable Logic Devicexe2x80x9d);
literature (3): (U.S. Pat. No. 5,629,637, xe2x80x9cMethod of Time Multiplexing a Programmable Logic Devicexe2x80x9d) and
literature (4): (U.S. Pat. No. 5,646,545, xe2x80x9cTime Multiplexed Programmable Logic Devicexe2x80x9d; all Trimberger et al., owned by Xilinx Inc., U.S.A., there is disclosed a method for time multiplexing a programmable Logic LSI.
However, there is much to be desired in the aforementioned art, which is discussed hereinbelow.
In the above publications, there is not disclosed means for storing an internal state of each of plural circuit configurations when these circuit configurations are used in a switching fashion on the same hardware.
If the internal sates of the respective configurations are not stored it becomes necessary to-perform an inherently unnecessary processing of activating a circuit until the internal state to re-initiate the processing is restored after a given circuit configuration is switched to another circuit configuration and reversion is again made to the first-stated circuit configuration.
For example, if plural stages of pipeline processing circuits are involved, it is necessary to start the operation as from the processing several cycles before a time point of switching the circuit configuration so that the status of respective stages will revert to a status which allows for re-initiation of processing. This necessitates a mechanism for operating the circuit several cycles thus increasing power consumption and processing time and leading to sophistication that a designer has to construct the circuitry taking this into consideration.
If there is necessity for employing the internal status saved in a certain circuit configuration in another circuit configuration, it was necessary to construct an internal memory circuit for saving the internal status to read out the internal status subsequently.
It is therefore an object of the present invention to provide a data holding circuit adapted for retreating and restoring the internal status.
It is another object of the present invention to provide a data holding circuit in which a circuit user is able to retreat and restore the internal status automatically without being conscious about such retreating or restoration.
It is still another object of the present invention to provide a data holding circuit in which the internal status can be retreated and restored only when such retreating or restoration is desired by the circuit user.
It is a further object of the present invention to provide a data holding circuit in which the sites in the memory portion or unit for data retreating or restoration can be determined automatically.
It is yet another object of the present invent ion to provide a data holding circuit in which it is possible to restore internal status selectively from the retreated internal status. Other objects of the present invention will become readily apparent from the following description and the claims.
According to a first aspect of the present invention, there is provided a data holding circuit having a data holding portion and a memory portion wherein at least one internal status of the data holding portion is retreated to the memory portion and wherein the internal status retreated to the memory portion is restored from the memory portion to the data holding portion.
According to a second aspect of the present invention, there is provided a data holding circuit having a data holding portion holding one-bit data and a memory portion
wherein at least one internal status of the data holding portion is retreated to the memory portion and the internal status retreated to the memory portion is restored from the memory portion to the data holding portion.
According to a third aspect of the present invention, a data holding circuit includes a data holding portion comprised of a flipflop circuit and a memory potion.
According to a fourth aspect of the present invention, there is provided a data holding circuit having a data holding port ion comprised of a flipflop circuit and a memory portion, wherein
a state of a flipflop on a master side or a flipflop on a slave side is retreated to the memory portion and
a state retreated to the memory portion is restored from the memory portion to the data holding portion.
According to a fifth aspect of the present invention, a data holding circuit has a data holding portion comprised of a latch circuit and a memory portion.
According to a sixth aspect of the present invention, a data holding circuit has a data holding portion holding data of plural bits and a multi-port memory portion.
According to a seventh aspect of the present invention, a data holding circuit has a non-synchronous data holding portion and memory portion.
According to an eighth aspect of the present invention, a data holding circuit in the first to seventh aspects includes a circuit unit (or means for) automatically determining storage elements constituting the memory port ion depending on the status of a circuitry including the data holding portion.
According to a ninth aspect of the present invention, the data holding circuit in the first to seventh aspects includes a circuit unit (or means) for automatically determining storage elements constituting the memory portion depending on changes in the structure of a circuitry including the data holding circuit.
According to a tenth aspect of the present invention, the data holding circuit in the first to seventh aspects includes a circuit unit (or means) for retreating the internal status to the memory portion at a time point when the retreating of the internal status of the data holding portion is necessary.
According to an eleventh aspect of the present invention, the data holding circuit in the first to seventh aspects includes a circuit module (or means) for restoring the internal status from the memory portion at a time point when the restoration of the internal status of the data holding portion is necessary.
According to a twelfth aspect of the present invention, the data holding circuit in the first to seventh aspects includes a circuit module (or means) for selecting whether or not the retreating of the internal status of the data holding portion to the memory portion or restoration from the memory portion is to be made.
According to a thirteenth aspect of the present invention, the data holding circuit in the first to seventh aspects includes a circuit module (or means) for retreating the internal status of the data holding portion to the memory portion in synchronism with clock signals and for restoring the internal status retreated to the memory portion to the data holding portion.
According to the fourteenth aspect of the present invention, in the data holding circuit in the preceding aspects control is performed so that a restoration operation from the memory portion and retreating to the memory portion will occur in the high and low status of the clock signals, respectively.
According to a fifteenth aspect of the present invention in the data holding circuit of the first to seventh aspects control is performed so that the restoration operation from the memory portion and retreating to the memory portion is caused to occur from cycle to cycle.
According to a sixteenth aspect of the present invention in the data holding circuit of the first to seventh aspects includes a circuit module (or means) for performing control so that the internal status of the data holding port ion is retreated to the memory potion and for restoring the internal status retreated to the memory potion to the data holding portion only when the retreating and restoration operations are necessary.
According to a seventeenth aspect of the present invention, the data holding circuit of the first to seventh aspects includes a circuit unit (or means) for selecting, from the memory potion, an internal state to be restored to the data holding portion among the internal states retreated to the memory potion.
According to an eighteenth aspect of the present invention, the data holding circuit of the first to seventh aspects includes a circuit module (or means) for restoring the internal status retreated to the memory potion to a data holding portion distinct from the data holding portion to which the data has been retreated.
According to a nineteenth aspect of the present invention, the data holding circuit of the first to seventh aspects data is previously written in the memory potion, wherein the data stored in the memory potion is set in the data holding portion on startup of operation of the data holding circuit and on modifying a portion in use of the memory potion to determine an initial output value.
Further aspects of the present invention will become apparent from the entire disclosure including the embodiments, claims, and drawings. Particularly, the features of set out in the claims are incorporated herein by reference thereto.